1. Field of the Invention
The inventions claimed herein relate in general to semiconductor memory devices. More specifically, the claimed inventions relate to circuit arrangements for driving a sense amplifier for use with semiconductor memory devices. A sense amplifier is caused to achieve a high sensitivity by increasing a voltage difference between a data I/O line and a complementary data I/O line.
2. General Background and Related Art
In a semiconductor memory device, data read out from a specific memory cell is transferred via a data input/output (I/O) line pair to a sense amplifier. The sense amplifier senses and amplifies a small voltage difference between the to lines of the data I/O line pair and outputs an amplified signal that has a predetermined logic level.
FIG. 1 (Prior Art) is a block diagram showing a conventional semiconductor memory device arrangement 10 containing a two-stage sense amplifier structure. The conventional arrangement of a semiconductor memory device includes a memory cell 11, a first sense amplifier 12, a second sense amplifier 13 and a delay unit 14.
In a read operation, a data stored in the memory cell 11 is read out in response to a column select signal COLUMN_SELECT applied to the memory cell. The read data is applied to a data I/O line DB and a complementary data I/O line /DB. Then, the first sense amplifier 12, which is enabled in response to a sense amplifier strobe signal SA_STROBE, senses and amplifies a voltage difference between the data I/O line DB and the complementary data I/O line /DB to thereby generate an amplified signal.
The delay unit 14 delays the sense amplifier strobe signal SA_STROBE for a predetermined time to generate a delayed sense amplifier strobe signal. Then, the second sense amplifier 13 senses and amplifies the amplified signal in response to the delayed sense amplified strobe signal.
In the conventional semiconductor memory device 10 having the two-stage sense amplifier structure, the voltage difference between the data I/O line DB and the complementary data I/O line /DB are greatly increased through two sense amplifiers 12 and 13, si that an erroneous operation due to various noise factors can be effectively prevented.
However, since the second sense amplifier 13 is operated a predetermined time after the operation of the first sense amplifier 12, the operation speed of the semiconductor memory device is limited.